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MRF89XA
4.4.2
SUGGESTED PA BIASING AND
MATCHING
The recommended PA bias and matching circuit is
illustrated in Figure 4-5 .
FIGURE 4-5:
RECOMMENDED PA BIASING AND OUTPUT MATCHING
PARS
0.047 μF
100 nH
1W 1%
PA
RFIO
Low-pass and DC block
Refer to Section 4.7, Bill of Materials for the optimized
matching arrangement for each frequency band.
SAW
Antenna
port
DC block
4.4.3
COMMON INPUT AND OUTPUT
FRONT-END
FIGURE 4-6:
FRONT-END
DESCRIPTION
The Receiver and Transmitter share the same RFIO
pin (pin 31). Figure 4-6 illustrates the configuration of
the common RF front-end.
In Transmit mode, the PA and PA regulator are active,
with the voltage on the PARS pin equal to the nominal
voltage of the regulator (1.8V). The external inductance
is used to bias the PA.
PARS
PA
Regulator
(1.8V)
RX ON
In Receive mode, both the PA and PA regulator are
OFF and PARS is tied to ground. The RF choke induc-
tor is then used to bias the LNA.
To
Antenna
RFIO
PA
LNA
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 97
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